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Senior DFT Logic Design Engineer

Intel

Hillsboro, OR (+ Phoenix, Santa Clara) · RemoteFull-time$141,910 – $269,100 / yearly
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Job details

Pay

$141,910 – $269,100 / yearly

Job type

Full-time

Work setting

Remote / Hybrid

Location

Hillsboro, OR (+ Phoenix, Santa Clara)

Posted

Posted 7 days ago

Full job description

Intel Foundry seeks a Senior DFT Logic Design Engineer to support Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation flows. The role collaborates with customers, IP providers, and EDA vendors, creates application notes and training, drives block- and SOC-level DFT/DFM and ATPG methodology, and supports customer tape-outs, targeting aerospace, defense, and government applications. Hybrid role.

Qualifications

  • US citizenship and ability to obtain a US Government Security Clearance
  • Bachelor's degree in electrical/computer engineering, computer science, or another STEM field
  • 3+ years with advanced CMOS processes (16nm and below) and ASIC DFT/DFM insertion
SemiconductorAerospace

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